Samsung 3nm Chip Mass Production On Track To Start in Q2

Samsung 3nm Chip Mass Production On Track To Start in Q2

Posted on

Samsung on Thursday said that it is on track to start high-volume production using its 3GAE (3 nm-class gate all-around early) fabrication process this quarter (i.e., in the coming weeks). The announcement not only marks the industry’s first 3nm-class manufacturing technology, but also the first node to use gate-all-around field effect transistors (GAAFETs).

“Enhance technology leadership via world’s first mass production of GAA 3-nano process,” a statement [PDF] by Samsung reads.  

Samsung Foundry’s 3GAE process technology is the company’s first process to use GAA transistors, which Samsung officially calls multi-bridge channel field-effect transistors (MBCFETs).

(Image credit: Samsung)

Samsung formally introduced its 3GAE and 3GAP nodes about three years ago. When the company described its 256Mb GAAFET SRAM chip produced using its 3GAE technology, it made a number of claims. Samsung said that the process would enable a 30% performance increase, a 50% power consumption reduction, and up to 80% higher transistor density (including a mix of logic and SRAM transistors). It remains to be seen how the actual combination of performance and power consumption will play out for Samsung though.

(Image credit: Samsung)

In theory, GAAFETs have a number of advantages when compared to currently used FinFETs. In GAA transistors, channels are horizontal and are surrounded by gates. The GAA channels are formed using epitaxy and selective materials removal, which allows designers to precisely tune them by adjusting width of the transistor channel. High performance is gained via wider channels, low power via narrower channels. Such precision greatly reduces transistor leakage current (i.e., lowers power consumption) as well as transistor performance variability (assuming that everything works well), which means faster time-to-yield, time-to-market, and improved yields. Also, GAAFETs promise to reduce cell area by 20% – 30%, according to a recent presentation by Applied Materials.

(Image credit: Applied Materials)

Speaking of Applied, its recently introduced high-vacuum system IMS (Integrated Materials Solution) system for forming the gate oxide stack is meant to address a major challenge of GAA transistor manufacturing, a very thin space between the channels and necessity to deposit the multi-layer gate oxide and metal gate stacks around the channels in a very short period of time. The new AMS tool from Applied Materials can deposit gate oxide that is only 1.5 angstroms thick using atomic layer deposition (ALD), thermal steps, and plasma treatment steps. The highly-integrated machine also performs all necessary metrology steps.  

Source link

Leave a Reply

Your email address will not be published. Required fields are marked *