Intel HPC Roadmap: 800W Rialto Bridge GPU, Falcon Shores XPU, Ponte Vecchio with HBM Benchmarks

Intel HPC Roadmap: 800W Rialto Bridge GPU, Falcon Shores XPU, Ponte Vecchio with HBM Benchmarks

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Intel’s keynote at the International Supercomputing Conference came with a new roadmap as it works towards its daunting goal of delivering Zettascale-class performance by 2027. As you can see in Intel’s Super Compute Silicon Roadmap above, today’s announcements include the first details of Intel’s Rialto Bridge GPUs, the next generation of its yet-to-be-launched Ponte Vecchio GPUs. The Rialto Bridge data center GPUs will sport up to 160 cores fabbed on a newer process node, come with an obviously heavily-reworked architecture, operate at up to 800W, deliver up to 30% more performance in applications, and begin sampling in mid-2023.

Additionally, Intel shared more details about the Falcon Shores XPU, a chip that will feature a varying number of compute tiles with x86 cores, GPU cores, and memory in a dizzying number of possible configurations. Intel plans to combine its CPU and GPU product lines into this singular composable product, merging the two lineups into one in 2024.

We now also have the first benchmarks of Intel’s HBM-equipped Sapphire Rapids server chips working their way to market to contend with AMD’s Milan-X processors. Intel claims these chips offer up to three times the performance of their Ice Lake Xeon predecessors in memory throughput-limited applications.

Delivering on Intel’s Zettascale goal will require a series of advancements, many of them revolutionary, and today the company also shared some of its nearer-term goals while also sketching out the broader long-term plan with a Zettascale building blocks roadmap. Let’s dive into the announcements. 

Intel Rialto Bridge GPU and XPU Manager

Intel is sticking with naming its enterprise-class GPUs after Italian bridges, with the current-gen Ponte Vecchio followed by Rialto Bridge, Intel’s next-gen data center GPU that will come to market in 2023. Intel divulged that this chip would feature up to 160 Xe cores, a substantial increase over the 128 cores present on Ponte Vecchio.

As we can see above, while the Ponte Vecchio design consisted of 16 total compute tiles arranged in two banks that run down the center of the chip, with eight cores per tile, Rialto Bridge only has eight longer tiles with (presumably) 20 Xe cores apiece, signifying a significant design shift.

We also see that Ponte Vecchio’s Rambo Cache tiles have been removed, though there are still eight HBM tiles of an unknown flavor flanking the cores while two Xe Link tiles are arranged at opposing corners of the chip package. To help illustrate the differences, the final six images in the above album include block diagrams of the current-gen Ponte Vecchio design.

Rialto Bridge comes with a newer unspecified process node, but Intel hasn’t specified which components will get upgrades (presumably, all will move to newer nodes). Currently, Intel uses its ‘Intel 7’ node for Ponte Vecchio’s base tile and cache, TSMC 5nm for the compute tile, and TSMC 7nm for the Xe Link tile.

Rialto Bridge also comes with unspecified architectural enhancements, similar to a “tick,’ that confer up to a 30% performance improvement in applications over Ponte Vecchio. Intel hasn’t provided any benchmarks to back up those claims yet and we aren’t sure if those improvements are at the same clocks/power envelope. However, the 30% projection closely tracks the 25% increase in core count, implying we’re not going to see substantial IPC improvements.  

Intel lists Rialto Bridge’s peak power consumption at 800W, an increase over Ponte Vecchio’s 600W peak, and will be available in the Open Accelerator Module (OAM) form factor. Intel says it will adopt the OAM 2.0 spec, though it will also continue to offer its GPUs in other form factors. Rialto Bridge will be compatible with Ponte Vecchio packaging, so it can be a drop-in upgrade.

In addition, the company will soon launch its XPU Manager, an open-source monitoring and management software for its data center GPUs that can be used both locally and remotely. Otherwise, Intel only shared hazy details about this new GPU, using claims like ‘more FLOPs,’ ‘increased I/O bandwidth,’ and ‘More GT/s’ that don’t give us any insight into the new design. However, the company did include an IDM 2.0 listing in the slide, indicating that it will continue to use foundry partners for some of the Rialto Bridge tiles. We’re sure to learn more soon, though — Intel says Rialto Bridge will arrive in 2023.

Intel Falcon Shores XPU

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