Whatcookie, a software developer behind RPCS3, a multi-platform open-source Sony PlayStation 3 emulator, has released a patch that makes use of AVX-512 instructions and brings a 30% performance improvement to the emulator. So far, AVX-512 instructions have not made much sense for games. But in the case of a PS3 emulator, a large register file of AVX-512-enabled hardware, data level parallelism, and the LLVM compiler can do wonders.
But before jumping in to how AVX-512 instructions make sense for RPCS3, something that Whatcookie explained in his detailed blog post, let’s take a short dive in the recent history of computing.
When you need to emulate Cell, you need explicit parallelism and large file registers, a combination that AVX-512 CPUs feature. As it turns out, the LVVM compiler automatically chooses the best possible code path, which in case of AVX-512-enabled hardware means an appropriate code path. For obvious reasons (we are talking about emulation here at the end of the day) it is not exactly ideal, not all mask registers can be used, for example.
AVX-512 also adds new mask registers which can be optionally used with EVEX encoded instructions,” wrote Whatcookie. “There are new comparison instructions which generate a mask in the mask registers as the result of a comparison between vectors. When a mask register is used as an operand all of the elements not selected by the mask will either be zeroed or leave the existing value in the destination register untouched. There are 8 mask registers, through k0 – k7, however only k1 – k7 can be used to mask things out, as k0 implicitly behaves as if all elements are selected.”
Nonetheless, the numbers speak for themselves. A 30% performance uplift is significant. Some may ask why bother about this kind of optimization considering the fact that we are already at well above 120 frames per second on our best gaming CPU, Intel’s Alder Lake Core i9-12900K? The answer is that there will be lower power machines that will still benefit from this optimization.
When Sony introduced its PlayStation 3 based on the Cell CPU featuring one general-purpose Power core and eight synergistic processing elements (SPEs), a proprietary instruction set architecture with in order execution and 128-bit SIMD organization, the gaming industry was not exactly impressed since Cell was so much different than conventional processors of 2006. Something similar happened to Intel’s AVX-512 instructions introduced with its 2013 Xeon Phi ‘Knights Landing’ supercomputer accelerators and later added to Skylake-X desktop CPUs (and the appropriate generation of Xeon Scalable).
Thread level (multi-core/multi-thread) and data level parallelism (SIMD) are exceptionally good for high-performance computing (HPC), datacenter, encoding, and encrypting workloads, and even games, yet they are sometimes hard to exploit. Hardware base, code complexity, costs, time-to-market, and numerous other considerations drive decisions not to invest resources in development of software that would use every single client side CPU (or GPU) innovation that is out there. This approach to video games is considered good enough, which is one of the reasons why both Microsoft and Sony are on x86 (with AVX2, but without AVX-512) with a conventional Radeon graphics architecture.