TSMC on Thursday held a “Volume Production and Capacity Expansion Ceremony” at its Fab 18 in in the Southern Taiwan Science Park (STSP). Fab 18 is where production of chips using its N3 (3nm-class) process technology take place. The foundry says that yields of the 3nm chips it mass produces are good and that the family of its N3 technologies will serve its clients for many years to come.
N3 in HVM
TSMC reportedly initiated high volume manufacturing (HVM) on its N3 fabrication process in early September. By now the first batch of chips has been produced and tested, so the formal announcement about volume production is generally designed to show that the foundry’s 3nm-class process is good for mass production and chips made on it yield ‘good.’ For TSMC, N3 is a very important family of process technologies as it will be the foundry’s last general-purpose node based on FinFET transistors and a node that will serve its customers for at least 10 years. In fact, TSMC says that N3 and its successors will be used to build ‘products with a market value of $1.5 trillion within five years’ of HVM.
Compared to TSMC’s N5 manufacturing technology, the company’s N3 production node promises to deliver a 10% to 15% performance improvement (at the same power and transistor count), reduce power consumption by 25% – 30% (at the same frequency and complexity), and increase logic density by around 1.6 times. Meanwhile, N3 barely offers any SRAM scaling as it features an SRAM bitcell size of 0.0199 µm^², which is only ~5% smaller compared to N5’s 0.021 µm^² SRAM bitcell.
| Header Cell – Column 0 | N3E vs N5 | N3 vs N5 |
|---|---|---|
| Speed Improvement @ Same Power | +18% | +10% ~ 15% |
| Power Reduction @ Same Speed | -34% | -25% ~ -30% |
| Logic Density | 1.7x | 1.6x |
| HVM Start | Q2/Q3 2023 | H2 2022 |
Meanwhile, the first iteration of TSMC’s 3nm-class fabrication processes — N3 also known as N3B — is expected to be used by early adopters for select applications only as it reportedly has a rather narrow process window. This could translate into lower yields for certain designs. In fact, media reports say that the majority of TSMC’s clients are now lining up for N3E manufacturing technology that improves process window, increases performance, and further reduces power consumption, at the cost of SRAM scaling (i.e., lower transistor density). Apparently, N3E feature a a 0.021 µm^² SRAM bitcell, with little or no changes from N5. This will mean higher die sizes for SRAM intensive designs (the vast majority of CPUs, GPUs, and SoCs).
Meanwhile, N3 offers chip designers FinFlex, a powerful way to optimize die sizes and performance/power consumption of their chips. FinFlex lets developers to mix and match different kinds of standard cells within one block to accurately optimize performance, power consumption, and area, which will be particularly appreciated by designers of complex system-on-chips that tend to take advantage of both transistor performance and transistor density.
Eventually, TSMC plans to add more nodes to the N3 family. The newest versions of the process include N3P, which promises enhanced performance, N3S designed to increase transistor density, and N3X with enhanced voltages as well as further performance optimizations for applications like CPUs.
Customers Are Lining Up for N3 Despite High Costs
A rumor has it that virtually all of TSMC’s most important customers, including AMD, Apple, Broadcom, Intel, MediaTek, Nvidia and Qualcomm are all interested in using TSMC’s N3 nodes, though it is hard to tell when each of these chip designers jump on the foundry’s 3nm bandwagon and with which products. Apple is expected to be one of the first clients to adopt TSMC’s N3 for one of its premium SoCs, though we have no idea which SoC it is. Meanwhile, AMD intends to adopt N3 for some of its Zen 5-based products due in 2024, whereas Nvidia will likely use N3 for its next-generation Blackwell architecture-based GPUs due around the same timeframe.
But usage of TSMC’s N3 is not going to be cheap. Some reports say that the contract maker of chips could charge as much as $20,000 per wafer processed using its 3nm-class technology. TSMC’s pricing of course depends on many factors, such as volumes, designs, and specifications, so take the number with a grain of salt.
Meanwhile, high quotes mean that fabless chip designers may prefer to reserve TSMC’s leading-edge nodes for premium products while making more mainstream devices using a proven fabrication technology. For example, Apple uses TSMC’s N4 (4nm-class) manufacturing process only for its A16 Bionic that powers its flagship iPhone 16 Pro. By contrast, the company’s iPhone 14 non-Pro continues to rely on the A15 SoC from 2021 that is made on TSMC’s N5P technology.
Fab 18 Phase 8
In addition to announcing that its N3 process technology had entered HVM, TSMC also held topping ceremony of its Fab 18 phase 8 building. The company uses its Fab 18 to make its most advanced chips on its N5 and N3 production nodes. Once Fab 18 phase 8 is equipped with production tools, it will significantly expand TSMC’s capacity for. Its leading-edge fabrication processes.