TSMC Readies N2P and N2X: 2nm with Enhanced Performance

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At the 2023 North American Technology Symposium TSMC revealed more information about its upcoming 2nm-class process technologies set to be production ready in 2025 – 2026. The world’s largest foundry plans to expand its N2 family with N2P that will get a backside power rail and promises to boost performance, reduce power consumption, and increase transistor density. In addition, TSMC plans N2X, a node designed to deliver maximum performance and support for higher voltages.

(Image credit: TSMC)

N2 Provides Full Node Advantages

TSMC’s original N2 process technology, set to enter high volume production sometime in 2025, introduces gate-all-around (GAA) Nanosheet transistors. When compared to N3E, the new node promises to boost performance by 10% to 15% with an identical power and transistor count, or decrease power consumption by 25% to 30% while maintaining the same frequency and complexity. When it comes to scaling, TSMC refrains of providing detailed numbers, but says that the new fabrication technology will enable an increase of chip density by 15%, which is an ambiguous term as it reflects a hypothetical IC containing 50% logic, 30% SRAM, and 20% analog circuits. 

(Image credit: TSMC)

TSMC’s N2 progress looks to be as planned. At its symposium, TSMC announced that its Nanosheet GAA transistor performance had reached over 80% of its target specifications and that the average yield of a 256Mb SRAM test IC exceeds 50%.

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